One of the key building blocks found in most electronic equipment is the frequency synthesizer. The frequency synthesizer outputs an oscillator output which may be used for signal generation or signal mixing.
Signal mixing may be used for example in a receiver to down convert a received radio frequency signal to a baseband frequency signal in order that the modulating/information signal, in the received signal may be separated from the carrier signal. Similarly signal mixing may be used in a transmitter to up convert the information/modulating signal to the carrier frequency.
In a transmitter the modulating signal is formed in the base band frequency (i.e. around zero frequency). For example a phase of certain selected pulse form is modulated depending on the information that is to be transmitted. In a communication system using a radio channel to transmit the information, the base band signal is then up-converted to a radio frequency of the radio channel by mixing it with a local oscillator (LO) signal. In a direct conversion transmitter the mixing is carried out in one stage and the base band signal is therefore multiplied with a local oscillator signal which has a frequency determined by the radio channel used in that particular communication system. In a frequency domain representation this can be described as the base band signal being transferred from a zero frequency to the local oscillator frequency which in the case of the direct conversion transmitter is in the middle of the transmitted channel.
In a receiver the local oscillator is used to convert the received signal down in frequency from the received signal radio frequency to the base band (zero frequency) or intermediate frequency. In case of a direct conversion receiver the received signal is mixed to the zero frequency in a single stage. In this way the carrier component (i.e. the frequency component in the LO frequency band) of the received signal is removed and the synchronization to the modulated base band signal is possible
Frequency synthesizers have traditionally been created using crystal oscillators, phase locked loops (PLL) consisting of voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO).
Digitally controlled oscillators (DCO) can be used in digital phase locked loops to create a controllable and tuneable frequency synthesizer such as the one featured in Golten's paper “Analog-Input Digital Phase Locked Loops for Precise Frequency and Phase Modulation”, IEEE transactions on Circuits and Systems—II; Analog and Digital Signal Processing, Volume 42, No 10, October 1995. This implementation shows where the conventional analogue phase locked loop circuit can be at least partially digitized by replacing the analogue loop filter with a discrete-time loop filter, the phase detector by a sampled phase detector, and the voltage control oscillator by a digitally controlled oscillator (DCO).
Implementations of the digital phase locked loops typically feature a time to digital converter (TDL) component which compares the timing of the input reference clock with the DCO output. The time to digital converter (TDC) can be for example a Vernier Delay Line (VDL). The Vernier delay line is an array of cells or stages, each stage receives the digitally controlled oscillator and reference signal output from a previous stage, delaying each input by a predefined delay period, detecting if there is a timing delay between the signals and outputting the delayed signal to the next stage.
The VDL implementations currently in use have problems in that a single VDL configuration can either provide high accuracy or short delay path but not both. For example if each delay element is designed to produce a delay resolution of 1 ps, then in order to cover a range of 500 ps 500 delay elements are required.
By creating a VDL implementation with this number of cells the VDL implementation requires a significant amount of silicon area on the integrated circuit. Also in order to drive the delay and comparison circuits in the long chain cell device requires a significant amount of current. This current thus results in high power consumption and requires extra cooling to dissipate the extra heat of such a circuit. Furthermore the implementation of long delay line may become difficult, due to high precision and matching requirements.
There have been some previous attempts to improve this problem. In U.S. Pat. No. 5,703,838, a Vernier delay line is provided with an interpolator which provides a precision level smaller than a clock period. It does so by delaying a periodic pulse signal on a delay line which has equal time spaced taps and with a total delay which has a harmonic greater than 1 pulse period.
However making equally spaced taps on input signal harmonics is challenging and requires for example a small PLL circuit (inside a PLL system) to be accurate.
US-20030006750 describes a single stage VDL structure used to mimic the behaviour of a chain of VDL stages. However, such an implementation cannot effectively operate in high resolution time digitalisation situations because it is impossible to implement the counter for very small delay feedback oscillators.